The present invention relates generally to the packaging of semiconductor devices and, more particularly, to an encapsulated chip scale package.
In the electrical industry, semiconductor devices (e.g., transistors, integrated circuit chips, and the like) are often permanently attached to the desired electrical circuitry by first connecting the miniature semiconductor device to a lead frame. The lead frame is then connected to the desired circuit. After the semiconductor device has been connected to the lead frame, the device may be tested to determine whether it has the requisite electrical and mechanical characteristics.
In addition, it is desirable to seal or otherwise package the semiconductor device and an area encompassing the ends of the lead frame so that the device resists environmental moisture and physical abuse. Such moisture and abuse may adversely affect the electrical properties of the device. In many conventional designs, semiconductor devices are sealed by using ceramic or metal enclosures that are relatively expensive and complicated to manufacture. Also, substantial labor is required to mount the device within the ceramic or metal enclosure and to connect external leads to the device. Increased costs and complicated manufacturing steps are to be avoided. Therefore, plastics (e.g., resins) are also used to encapsulate the semiconductor device and lead frame ends. Resin encapsulation is typically done in a controlled-humidity atmosphere after the semiconductor device has been bonded to the lead frame but before the lead frame is attached to further electrical circuitry.
An essential step in the fabrication of semiconductor device packages is the formation of electrical contacts to the device. For purposes of example, consider an integrated circuit chip as the semiconductor device. The chip is typically mounted on a support member, commonly termed a die paddle, and electrically contacted through leads from the lead frame. The leads extend to the area outside of the package.
As might be expected, several techniques have been developed for making good electrical contacts between the chip and the leads. One exemplary technique forms the contacts by wire bonding. In this technique, individual wires are attached to a lead and a corresponding site on the chip; i.e., there is one site on the chip for each lead. The wires are typically gold. Another exemplary technique bonds the leads directly to solder or gold bumps on the chip. The leads are typically on a metal tape with one set of leads for each chip. The latter technique of forming the contacts can be highly automated and, in its automated form, is generally referred to as Tape Automated Bonding (TAB).
U.S. Pat. No. 5,080,279 discloses a method of manufacturing packages using the step of bonding a plurality of leads to sites (i.e., contact pads) on a substrate. The bonding step includes the further steps of clamping the leads into contact with the pads using a plate; heating the pads and leads with a thermode held at constant temperature and in contact with the plate; monitoring the temperature of the plate and removing the thermode from the plate when the material of the pads has melted; and removing the plate from the leads when the material has cooled sufficiently to form bonds. In a preferred embodiment, the pads are solder. In a further preferred embodiment, the substrate is an integrated circuit chip. In another embodiment, the substrate is a printed wiring board.
Thus, the method described in the ""279 patent may be used to attach a surface mount integrated circuit package to a printed wiring board. Such an assembly is depicted in a sectional view in FIG. 3. FIG. 3 shows a printed wiring board 31, a lead frame 33, an integrated circuit chip 35, an encapsulation 37, leads 39, a clamping plate 41, a thermode 43, and bumps 45 attaching leads 39 to printed wiring board 31. The portion of thermode 43 that contacts clamping plate 41 has a flat face; thermode 43 has a small cavity in which lead frame 33 and chip 35 fit together with associated elements. The bumps 45 are located on the printed wiring board 31.
The method disclosed by the ""279 patent has several disadvantages. First, relatively long leads 39 connect the chip 35 to the printed wiring board 31 external to the chip package. Leads 39 are attached to lead frame 33 at the periphery of the chip package, and only indirectly to chip 35. This configuration creates undesirable parasitic inductance. Second, relatively complex structure is required to connect leads 39 to printed wiring board 31: thermode 43, clamping plates 41, and bumps 45.
The deficiencies of the conventional semiconductor packages show that a need still exists for an improved semiconductor package. To overcome the shortcomings of the conventional packages, a new semiconductor package is provided. An object of the present invention is to eliminate wire bonds. Another object is to attach the semiconductor device directly to the lead frame. A related object is to avoid the need for a die paddle on the lead frame. Still another related object is to minimize package parasitics, including lead frame capacitance and inductance and bond wire inductance.
Yet another object of the present invention is to provide a semiconductor package that allows minimal package size. A further object of the present invention is to provide a built-in thermal slug capable of thermal dissipation. Still another object of the present invention is to assure good RF performance, equivalent to flip chip attach, while providing a plastic package for conventional surface mount technology handling techniques and eliminating handling concerns prevalent with the bare silicon and underfill process.
To achieve these and other objects, and in view of its purposes, the present invention provides a chip scale package with outer dimensions for housing of semiconductor devices to facilitate handling, testing, and later attachment of the devices to further electrical circuitry. The chip scale package has four main components: a semiconductor device, a lead frame, a connection between the semiconductor device and the lead frame, and an encapsulation sealing the semiconductor device from the surrounding atmosphere. The semiconductor device has a body, an active surface, and outer dimensions that are between about 70% and 80% of the outer dimensions of the chip scale package. The lead frame has ends extending less than about 0.2 mm beyond the body of the semiconductor device and a solderable surface directly in line with and perpendicular to the surface of the integrated circuit, thereby minimizing parasitic inductance and capacitance, and a thermal slug removing heat from the semiconductor device with minimal thermal resistance.
Preferably, the semiconductor device is an integrated circuit chip. The connection between the semiconductor device and the lead frame is achieved, also preferably, using controlled-collapsed-chip-connection (C4) bumps. The C4 bumps electrically and mechanically connect the lead frame directly and without intervening structure to, and flush with, the entire active surface of the semiconductor device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.